1. Field Related to the Invention
The present invention concerns a method for manufacturing a semiconductor, and in particular a method for manufacturing a two-layered structure of a nonvolatile semiconductor memory.
2. Description of the Related Art
In the memory cell array of a nonvolatile semiconductor memory, there is a structure which contains a two-layered gate structure comprising a floating gate, which is electrically insulated from the periphery, in addition to a control gate of a usual gate.
The structure of the nonvolatile memory, which includes the conventional two-layered structure, is described in FIG. 1.
Cell gate oxide film 83 (about 100 angstrom thick) is formed on the surface within the region enclosed by field oxide film 82, which is formed on semiconductor substrate 81. Floating gate 84 (about 1000 angstrom to 2000 angstrom thick) is formed on cell gate oxide film 83. An ONO (oxide/nitride/oxide) insulation film 85 containing a three layer structure, such as a silicone oxide film/silicone nitride layer/silicone oxide layer or 50-60 angstrom/60 angstrom/50-60 angstrom, respectively, is formed on floating gate 84. A control gate 86 of polysilicon WSi 2000 angstrom/1200 angstrom is then formed on insulation film 85, which forms a MOS transistor.
When electrons are involved in floating gate 84, the channel cannot be easily induced by the negative charge of electrons, even if a word line attains a high voltage, because the threshold voltage rises too high to turn on the transistor. When electrons are not involved in floating gate 84, however, a high voltage applied to control gate 86 turns on the transistor if the word line attains a high voltage.
On the other hand, electrons can be accumulated in floating gate 84 by regulating the voltage applied to control gate 86 and a drain region (not depicted in the Figures). Floating gate 84 is formed by diffusing an N-type impurity, for instance, phosphorus, to attain a uniform density after deposition of polysilicon.
A bottom oxide film, corresponding to a silicon oxide film of the lowest layer for ONO insulating film 85, is formed by oxidizing polysilicon by thermal oxidation, where the impurity pertaining to floating gate 84 is diffused. This oxidation should proceed at a high temperature of about 850.degree.-1000.degree. C. in order to obtain sufficient insulation characteristics and charge storage characteristics. This process uses ONO insulating film 85 in three layers, which have, for instance, enhanced charge storage characteristics, rather than formation with the single silicon oxide film layer only.
However, when the memory cell is formed using the above-mentioned method, phosphorus within floating gate 84 is diffused into the cell gate oxide film through the route shown by arrow 1 in FIG. 1 in the course of the oxidation process for the bottom oxide film, which results in structural damage within the cell gate oxide film. Moreover, it invokes a problem concerning reliability due to an increase in the leak current.
Furthermore, because floating gate 84 is formed through the route indicated by arrow 2 in FIG. 1, phosphorus in polysilicon is diffused into the bottom oxide film during oxidation of polysilicon, which results in the degradation of the bottom oxide film quality.
Also, the oxidation rate for polysilicon containing abundant phosphorus is quickened by an accelerating phenomena, which causes a problem in the film thickness controllability. This controllability problem makes it difficult to form the oxide film with a desired thin film thickness.
In the preprocess used in forming the bottom oxide film, a polysilicon surface containing phosphorus is flooded with some liquid during a chemical process, e.g. wafer cleaning process, or exposed to an atmosphere, which brings up oxidation. As a result, rough natural oxide film is formed. In such a thick region, where the bottom oxide film thickness exceeds 10 nm, the influence of the above-mentioned natural oxide film can be ignored. However, when the bottom oxidation film thickness must be minimized to less than 10 nm, corresponding to a micronization of devices, a poor quality natural oxidation film, 2 to 3 nm thick, cannot be ignored. Thus, countermeasures must be taken.
The natural oxide film is formed before the oxide film deposition, even with the LP-CVD (Low Pressure-Chemical Vapor Deposition) chamber being about 700.degree. C. The temperature of 700.degree. C. is the usual temperature when the bottom oxide film is formed by the LP-CVD method.
These natural oxide films change the film quality and the film thickness according to exposure time and process conditions of the wafer, which deteriorates the film thickness and the film quality control of the bottom oxide film.
In addition, the natural oxide film does not have a proper film quality, which results in the degradation of the bottom oxide film quality. This degradation often results in an insulation resistance, etc.
As mentioned above, a problem in the conventional semiconductor memory is the degradation in the cell gate oxide film quality due to the effects of phosphorus in the floating gate, which results in less reliability. Another problem is the lack of controllability in forming the bottom oxide film makes it difficult to achieve excellent film quality having a desired thin film thickness.